Software Engineer
Huawei Technologies Canada Co., Ltd (2023-)
Engaged in the development of FPGA CAD tools using C++20 for Place and Route team:
- Conducted thorough research to identify cutting-edge EDA algorithms tailored to support custom architectures, and developed multiple algorithms focusing on core routing, parallel scheduling and filter generation, leading to a notable 12x acceleration in router flow through the implementation of parallel techniques.
- Designed the complete clock solution for the tool, achieving a significant 16x speed enhancement compared to the previous solution for placing and routing on the clock network.
- Collaborated closely with the Timing team to pioneer advancements in clock skew optimization and the resolution of hold violations, resulting in a noteworthy 5\% increase in fmax.